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Digital Drive Upsamplers, DACs, jitter, shakes and analogue withdrawals, this is it. |
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Digital Drive Upsamplers, DACs, jitter, shakes and analogue withdrawals, this is it. |
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In Reply to: Re: Right :) posted by Ted Smith on July 29, 2006 at 06:50:17:
Hi Ted,The S9000ES has two clocks near the VC24+ chip (45 and 49M), but also 3 PLLs to provide clocks for the DSPs on the transport.
Even if you send a reference clock from the DAC to the transport, it still hits PLLs on the DSP board. So the clocks used for the PCM and DSD Decoders come from PLL. That is also the case with Philips.
What good is a low jitter clock next to a DAC if this same DAC is fed up data and clocks from a DSP that is being clocked with large amount of jitter? I would even say that with the bitstream DACs (delta sigma) the jitter is not of such a big concern at all. That DSP needs the precision clock, not the DAC. As you know, the DSD1700 DAC does not even need master clock since it is nothing more but FIR. This applies for all the latest BB DACs when in DSD mode.
Regards,
Alex
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Follow Ups
- Re: Right :) - Alex Peychev 14:46:58 07/29/06 (3)
- Re: Right :) - Ted Smith 15:00:29 07/29/06 (2)
- Re:I think you guys need a P(i)LL * - .Guy 23:45:12 07/29/06 (1)
- :) [nt] - Ted Smith 09:05:53 07/30/06 (0)
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