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Re: Right :)

"As Christine and Ted have mentioned, slaving the source to the
DAC clock is the best way of minimizing jitter"


I would have to disagree, even if you have flags telling you where the clock/s should fall. This was implemented in S/PDIF many moons ago too. :) Also, today's CD/SACD and Universal players need much more than ONE clock, and even if it is a 44.1K product only, it is still done with PLL/s. Referencing this PLL (which usually has enormous amount of jitter due to its design) with an external clock (from the DAC) will reduce the problem, but will not solve it. Not to talk about the fact that most of the clock syncing circuits today are based on VCO or VCXO.

I tried to explain this to Christine not long ago, but she didn’t get it. For example, the 44.1K ONLY Sony SCD-1/777ES has TWO PLLs inside. :)

Not that PLLs are bad! In fact, some later ones feature considerably lower jitter, may be the lowest obtainable (if synchronous operation is required, of course). :)

Regards,
Alex

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