In Reply to: Re: Sweetness VS Load Lines posted by Naz on August 9, 2006 at 00:38:55:
Look at the first two graphs. The second graph is out of phase with the first. The third 1K graph (the output of the second stage) is out of phase again. They are and are shown as inverting stages. Two inverting stages so the output of the total circuit is back in phase with the input.But that's not the point. If both stages have the same internal relationship between the fundamental and the distortion no canceling will take place. Please read my next post.
If the first stage's internal relationship between the fundamental and the distortion is 0 degrees and the second stage's internal relationship between the fundamental and the distortion is 180 degrees then there is cancellation. But you said that every stage has a 0 degree relationship between the fundamental and it's distortion at the output. If that were so no calcellation would take place.
You keep talking about how each stage inverts phase and the output of the second stage is out of phase with the output of the first stage and you are right but that does not cause calcellation. Look at my graphs one more time please. They do not show gain, just phase (except where I tried to show the distortion adding.) Please look again.
Mr. Lima explains this all very well.
Thanks...Tre'
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Follow Ups
- Re: Sweetness VS Load Lines - Tre' 01:05:48 08/09/06 (10)
- Re: Sweetness VS Load Lines - Naz 01:59:48 08/09/06 (9)
- Re: Sweetness VS Load Lines - Tre' 08:48:04 08/09/06 (8)
- Re: Sweetness VS Load Lines - Naz 21:17:40 08/09/06 (7)
- Re: Sweetness VS Load Lines - Tre' 07:55:16 08/10/06 (6)
- Re: Sweetness VS Load Lines - Naz 08:07:30 08/11/06 (5)
- Re: Sweetness VS Load Lines - Tre' 13:22:49 08/11/06 (4)
- Re: Sweetness VS Load Lines - Naz 19:05:07 08/11/06 (1)
- Post above is out of sequence ... should be last for this thread! - Naz 21:43:39 08/12/06 (0)
- Re: Sweetness VS Load Lines - Naz 15:57:54 08/11/06 (1)
- Re: Sweetness VS Load Lines - Tre' 17:37:32 08/11/06 (0)