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Digital Drive Upsamplers, DACs, jitter, shakes and analogue withdrawals, this is it. |
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Digital Drive Upsamplers, DACs, jitter, shakes and analogue withdrawals, this is it. |
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In Reply to: Appears to be a frequency-locked loop... posted by andy_c on August 2, 2006 at 11:02:19:
HowdyThat's why I was careful early on to talk about PLLs and their moral equivalents, but later got lazy (since no one was paying attention to details anyway) and jut talked about PLLs.
There are many ways of locking onto a clock using various forms of feedback to adjust the output clock (especially when you put a microprocessor with code in the loop, heck we had the clock of the microprocessor run off of the output clock in one of our designs, you'd better not screw up when you loose lock in that case :) Other designs than simple PLLs will affect jitter differently and aren't as easy to categorize or analyze, but there is always some jitter leakage, you just want to pick the form that's least audible on the other side of the DAC.
-Ted
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Follow Ups
- Re: Appears to be a frequency-locked loop... - Ted Smith 13:37:35 08/02/06 (1)
- The huge buffer approach in action - that's, my name 01:47:28 08/04/06 (0)
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