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You're really not getting this

In order for you to make sense of these discussions, you need to understand a few things. First, jitter creates distortion in the analog output of a DAC even when all the bits arrive perfectly. This makes the jitter problem in digital audio fundamentally different than the jitter problem in a computer interface. In a computer interface, jitter need only be controlled to a degree that guarantees reliable transmission of the bits. In a DAC, jitter must be more stringently controlled because it pollutes the analog output. Second, you need to understand what a phase locked loop is and it's obvious from your comments that you don't.

I'm going to summarize the four approaches to clocking an external DAC that were discussed in the previous threads. I don't know enough about this stuff to give you a comprehensive explanation, but hopefully this will give you a starting point to explore from.

1. Source-synchronous clocking

This is the simplest and poorest performing approach. A single PLL is used to lock onto the source clock which is embedded in the received data. The clock derived from this PLL is used to clock the DAC. The loop bandwidth must be wide enough to achieve and hold a lock on a source signal which may be quite noisy, which means there is little jitter filtration at the frequencies of interest to audio. However, this approach is generally good enough for computer interfaces.

2. Reclocking with a FIFO

This approach uses a dual stage PLL with a FIFO buffer in the second PLL. The first PLL is used in the manner described above to extract a clock from the source data. Data is clocked into the FIFO using this first clock. The DAC has its own (presumably higher accuracy) local clock reference. The local clock reference, along with the clock from the first PLL, are inputs to a second PLL. From these inputs, the second PLL derives a third clock which is used to clock data out of the FIFO. The second PLL varies the output clock to keep the buffer half full. One important aspect of this approach is that the output clock is not totally independent of the source clock - the degree to which jitter passes through from the source to the output of the FIFO buffer depends on the loop bandwidth of the PLLs. A lower loop bandwidth results in more jitter being filtered out, but it will be harder for the PLL to lock onto the source and it will be less able to handle transients, so there is a practical limit. Additional PLL/buffer stages can filter out more jitter, but add yet more latency, complexity, and cost.

3. Resampling with ASRC

Typically implemented on a chip, an ASRC accepts independent and asynchronous input and output clocks. Internal processing is typically driven by a master clock which may be identical to the input or output clock or independent from both. The source data is interpolated on input and then resampled at output rate using digital filters. In this approach, data in != data out. Input clock jitter may not affect the output clock, but it can affect the interpolated data.

4. A single master clock

This is the approach used by Ted's EMM gear, some pro audio gear, and some other types of non-audio instrumentation. In this approach, a single high precision master clock is used to drive both the transport and DAC. This approach focuses on avoiding jitter in the first place rather than supressing it later on. The only downside I can think of is that clock buffers add jitter, and in order to use a single master clock you may need to buffer the clock in each component. So you may not be able to avoid the PLLs.

Dave


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