In Reply to: Re: Test bench posted by Dave Kingsland on July 30, 2006 at 09:54:35:
This is an exaggeration. A well proportioned FIFO buffer can avoid compromising the new clock. In the real world this requires only very small shifts in master clock speed to avoid under-running the buffer. This strategy is particularly effective with high frequency jitter and the pitch shift is inaudible. Of course buffer size and clock adjustment strategies are critical to ensure proper management of lower and higher frequency jitter. That is probably why for instance the Benchmark sounds so good. A weak PLL design will let the clock follow LF jitter –which is very audible-- and pass it into the DAC.For the n-th time. You can say all you want from a theoretical tower of ivory. But look at the jitter rejection numbers of a DAC like the Benchmark, look at what it costs, and then it's clear that from an audiophile standpoint this is a solved problem. Perhaps it will be the progress bottleneck one day but it certainly is not now.
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Follow Ups
- Re: Test bench - Bertie_Livingston 14:16:06 07/30/06 (4)
- Re: Test bench - Dave Kingsland 17:26:24 07/30/06 (3)
- Re: Test bench - Bertie_Livingston 05:07:40 07/31/06 (2)
- Re: Test bench - Dave Kingsland 06:59:08 07/31/06 (1)
- Re: Test bench - Bertie_Livingston 09:30:36 07/31/06 (0)