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Re: Is Lavry DA10 genuinely an SRC or ASRC?

Howdy

If it's synchronous it does indeed have to be directly derived "synchronously" from the input clock. Usually in small integer ratios, e.g. upsampling from 44.1 to 88.2, 176.4, etc. You can do any integer ratio by first upsampling then downsampling.

To get rid of jitter you may use a local clock and buffer, but since you are synchronous you never have to worry about getting too far ahead or behind so you never need to resample the input data or interpolate it.

It is definitely the case that asynchronous input and output clocks imply that you have to do ASRC. I speculate that one of the benefits of picking a specific output clock freq and doing ASRC to it are that you can better control the jitter and other clock accuracy with a fixed rate clock and you can also better control the accuracy and resolution of a fixed freq reconstruction filter. Also by choosing a output clock that's weird, i.e. not near simple integer ratios of the input clock, you avoid the phasiness (flanging) you get as the input and output clocks go in and out of phase, well actually you sort of whiten it. Whether these make up for the degradation of the input data would depend on the implementation.

Just as a refresher of SSRC, conceptually you upsample by the numerator of your ratio, then filter out everything over 1/2 of the lowest of the input clock rate and the output clock rate and then down sample by the denominator. To upsample you can just put in zero samples between the real samples, e.g. to upsample by 55 you put in 54 zero samples between each input sample. To downsample you throw away the samples you don't want, e.g. to downsample by 47 you throw away 46 of every 47 samples. Clearly there is a lot of math to be saved by not calculating the samples you don't use and also you can take advantage of all of the zeros in the input to save work on the filter. So if you are SSRC by 55:47 there have to be 55 output clock cycles for each 47 input clock cycles.

-Ted

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