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Digital Drive Upsamplers, DACs, jitter, shakes and analogue withdrawals, this is it. |
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Digital Drive Upsamplers, DACs, jitter, shakes and analogue withdrawals, this is it. |
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In Reply to: OK, see you in a couple of months :-) posted by Scrith on October 27, 2006 at 09:22:51:
HowdyThen you loose much of your jitter reduction, TANSTAAFL.
The original issue was I2S vs. S/PDIF.
In I2S there is an explicit clock line, that clock could be used to drive the DAC proper directly with no requirement for buffering or any clock recovery (well maybe with with a little reconditioning but no PLL.)
With S/PDIF the clock is encoded in the data implicitly and (even with fairly smart) decoding is too jittery to directly drive a DAC: a buffer and some moral equivalent of a PLL is required to get a good enough clock to drive the DAC proper.
As we've talked about in the past a more ideal solution is for the DAC to provide the master clock to the transport so that the the PLL (or it's equivalent) isn't necessary for generating a clock for the DAC (it already would have the high quality clock.) When you work out the details a PLL is still necessary to receive the S/PDIF signal, but since you know that its average rate isn't going to diverge too far from the master clock you have in hand you can avoid all of the clock control issues in your local buffer handling.
-Ted
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- :) - Ted Smith 09:40:09 10/27/06 (0)
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